1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with an error correction function.
2. Description of the Related Art
Semiconductor memory devices with error checking and correcting (ECC) circuits are known. The ECC circuit has a function for checking whether data bits read from a memory cell array include error data, and correcting error data, if there is any. When a semiconductor memory device has the ECC circuit, it is highly reliable.
To correct error data, the ECC circuit uses, for example, parity bits. The parity bits are stored in the memory cell array of the memory device, independently of data. Based on computation using both the parity bits and data, the ECC circuit detects and corrects error data contained in the data.
The larger the number of data bits corresponding to one parity bit, the less the number of the required parity bits. Accordingly, a greater number of data bits than those input to or output from the memory are read therefrom, and the read data bits are checked and corrected by the ECC circuit. Part of the corrected data bits are output.
Specifically, during data reading, syndrome bits are generated from the parity bits and read data. Using the syndrome bits, it is checked whether the read data contains an error. If there is an error, the data is corrected, and part of the corrected data is output.
In contrast, during data writing, reading is performed before data is written. When the number of data bits corresponding to parity bits is greater than that of input data bits, part of data bits read from the memory are added to the input data bits, and parity bits are generated for the thus-obtained data bits (write data bits). Part of the corrected read data bits, input data bits and parity bits are stored in the memory.
Since during data writing, it is necessary to regenerate parity bits after data correction, the time required for computation for ECC is longer than the time required for computation during data reading. The computation for ECC during writing inevitably lengthens the time (write cycle time) required for writing.
Jpn. Pat. Appln. KOKAI Publication No. 11-16389, for example, discloses a technique, related to the above, for enhancing the accuracy of detection of a data error.